The present invention relates generally to logic circuits and, more particularly, to high-speed flip-flop flop circuits and designs.
FIG. 1A shows a schematic diagram of one embodiment of a typical prior art flip-flop circuit 100. As seen in FIG. 1A, prior art flip-flop circuit 100 included the significant elements: delay portion 101 with delay output terminal 113 carrying the signal L1_CLKd 121, also referred to herein as CLKd 121; first node 103; clock input terminal 102 coupled to signal L1_CLK 111, also referred to herein as CLK 111; data input terminal 104 coupled to data signal 107; second node 115 carrying signal end 125; second supply voltage 109, also referred to herein as ground 109; third node 114 carrying the signal OUT_n 123; and output terminal 116 carrying the signal output signal q_1127.
As also seen in FIG.1A, prior art flip-flop circuit 100 included delay portion 101 incorporated in prior art flip-flop circuit 100 to delay the incoming signal CLK 111 to ensure that a sufficient time was allowed for first node 103 to discharge to ground 109, through path 105, when the data signal 107 was a digital xe2x80x9c1xe2x80x9d. If this delay time was not sufficient, a racing condition could develop and the operation of prior art flip-flop circuit 100 would be impaired and/or functional failure of prior art flip-flop circuit 100 could result. Consequently, in the prior art, designers had to be extremely careful to ensure the delay time, also called the evaluation xe2x80x9cwindowxe2x80x9d provided by delay portion 101 was sufficient. However, a larger evaluation window resulted in longer hold times that may cause function error at the block level. Consequently, there was an inherent conflict between obtaining the minimum hold-time of operation for prior art flip-flop circuit 100 and providing a comfortable window to ensure proper operation of prior art flip-flop circuit 100.
In the prior art, the evaluation window or delay time of prior art flip-flop circuit 100 was identical and constant, regardless of the data input. This is seen in FIG. 1A by the fact that delay portion 101 is simply a two inverter delay of signal CLK 111, regardless of the state of the data signal 107. This feature of prior art flip-flop circuit 100 is also shown in FIG. 1B. FIG. 1B is a typical timing diagram for a prior art flip-flop, such as prior art flip-flop circuit 100. Shown in FIG. 1B are: the signal L1_CLK 111, also referred to herein as CLK 111, on clock input terminal 102 in FIG. 1A; data signal 107 on data input terminal 104 in FIG. 1A; the signal L1_CLKd 121, also referred to herein as CLKd 121, on delay output terminal 113 in FIG. 1A; the signal OUT_n 123 on third node 114 in FIG. 1A; the signal end 125 on second node 115 in FIG. 1A; and output signal q_1127 on output terminal 116 in FIG. 1A.
As shown in FIG. 1B, and discussed above, there existed delays or evaluation windows, i.e., windows 131, 141, 151, 161, 171 and 181 in FIG. 1B, between the fifty percent of the rising edge of the signal L1_CLK 111, i.e., points 133, 143, 153, 163, 173 and 183 in FIG. 1B, and fifty percent of the rising edge of the signal L1_CLKd 121, i.e., points 135, 145, 155, 165, 175, and 185 in FIG. 1B. Significantly, as shown in FIG. 1B, windows 131, 141, 151, 161, 171 and 181 were all of approximately equal duration, regardless of the state, i.e., high or low, of data signal 107. Therefore, windows 141, 151 and 181, when data signal 107 was high, were of approximately equal size as windows 161 and 171, when data signal 107 was low
The fact that evaluation windows 131, 141, 151, 161, 171 and 181 of prior art flip-flop circuit 100 were all of approximately equal duration, regardless of the state of data signal 107, was inefficient because when data signal 107 was high, or a digital xe2x80x9c1xe2x80x9d a long evaluation widow was required to delay signal CLK 111 so, as discussed above with respect to FIG. 1A, node 103 could discharge to ground 109 before the next clock. However, when data signal 107 was low, or a digital xe2x80x9c0xe2x80x9d, there is no need for a long evaluation window because node 103 does not discharge to ground 109 and therefore there is no need of the window to delay signal CLK 111. Consequently, in the prior art, evaluation windows 161 and 171 were unnecessarily large when the data signal 107 was a digital xe2x80x9c0xe2x80x9d. This, in turn, resulted in unnecessarily long hold times and inherent internal margins for prior art flip-flops such as prior art flip-flop circuit 100.
In addition, since, in the prior art, evaluation windows 131, 141, 151, 161, 171 and 181 were all of approximately equal duration, regardless of the state of data signal 107, there was an inherent, and static, internal margin. Consequently, when a circuit designer was modifying a prior art system incorporating prior art flip-flops, for instance in the event of a scaling or xe2x80x9cshrinkxe2x80x9d to a new generation, the designer would have to redesign each circuit and modify the layouts to ensure proper prior art flip-flop operation and that the internal margins were still satisfied. This was a huge effort and was an unfortunate waste of considerable time and resources that served to undermine the advantages inherent in the shrinking process.
Also, since, in the prior art, evaluation windows 131, 141, 151, 161, 171 and 181 were all of approximately equal duration, regardless of the state of data signal 107, evaluation windows 131, 141, 151, 161, 171 and 181 had to be large enough to accommodate the greatest possible number of operational parameters, i.e., prior art flip-flops, like any circuit, had to be designed to be flexible enough to operate in all, or most, technical corners anticipated. Since, in the prior art, evaluation windows 131, 141, 151, 161, 171 and 181 were all of approximately equal duration, this meant the entire system had to be designed with evaluation windows 131, 141, 151, 161, 171 and 181 large enough to accommodate the worst case. This, of course, was far from efficient and resulted in unnecessarily long hold times and unnecessary delay elements in the block which wastes very limited, and precious, chip space.
In addition, since, in the prior art, evaluation windows 131, 141, 151, 161, 171 and 181 were all of approximately equal duration, regardless of the state of data signal 107, and there was an inherent internal margin, prior art flip-flops were often not operational at ultra low supply voltages. In an electronics industry that stresses portability, prolonged battery function and minimization of heat generation, this was a significant limitation.
What is needed is a method and apparatus for creating a modified high-speed flip-flop that is capable of adjusting the delay time, or evaluation window, to accommodate the state of the data signal, thereby minimizing the hold time and eliminating the internal margin.
The present invention is directed to a method and apparatus for creating a modified high-speed flip-flop including a data selective adjustable evaluation window, thereby eliminating the internal margin.
According to the present invention, the evaluation window or delay time of the modified high-speed flip-flop circuits of the invention are self-adjusting and data selective. Consequently, the evaluation window is longer when the data signal is a digital xe2x80x9c1xe2x80x9d and significantly shorter when the data signal is a digital xe2x80x9c0xe2x80x9d. Therefore, the evaluation windows of the modified high-speed flip-flop circuits of the invention are variable so there is minimal hold time, increased efficiency and no opportunity for the creation of a racing condition. Consequently, the modified high-speed flip-flops of the invention are more robust than prior art flip-flops.
Since, according to the invention, the evaluation window is adjustable and data selective, there is no inherent internal margin. Consequently, when a circuit designer wishes to modify a system incorporating the modified high-speed flip-flop circuits of the invention, for instance in the event of a scaling or xe2x80x9cshrinkxe2x80x9d to a new generation, the designer can do so without the need to redesign each circuit and modify the layouts to ensure proper flip-flop operation. Thus, the modified high-speed flip-flop circuits of the invention are readily scalable and the huge effort and waste of time and resources required with prior art designs is completely avoided.
Also, since, according to the invention, the evaluation window is adjustable, and data selective, the evaluation window need not be large enough to accommodate the greatest possible number of operational parameters, i.e., the modified high-speed flip-flop circuits of the invention, with their adjustable evaluation window, are flexible enough to be adjusted to operate in all, or most, technical corners on a case by case basis. This means that, in contrast to the prior art designs, the entire system need not be designed with an evaluation window large enough to accommodate the worst case. Consequently, the modified high-speed flip-flop circuits of the invention are far more efficient, have shorter hold times and more robust than prior art flip-flops.
In addition, since, according to the invention, the evaluation window is adjustable and data selective and there is no inherent internal margin, the modified high-speed flip-flop circuits of the invention can be made operational at ultra low supply voltages. As noted above, in an electronics industry that stresses portability, prolonged battery function and minimization of heat generation, this is a significant advantage.
It is to be understood that both the foregoing general description and following detailed description are intended only to exemplify and explain the invention as claimed.